The present invention relates to a method for manufacturing a semiconductor substrate that constitutes a semiconductor device and in particular, it relates to a method for manufacturing a dielectric isolation substrate.
In an integrated circuit device in which the withstand voltage among the elements is high (power IC), it is necessary to insulate the individual elements that are to be integrated from one another. Publications such as JP/A/61-292934, IEEE ISPSD 1992 pp. 316-321 and the like disclose methods for manufacturing bonded type dielectric isolation substrates that achieve such a semiconductor device structure.
The following is an explanation of a method for manufacturing a bonded type dielectric isolation substrate in the prior art as disclosed in the publications mentioned above in reference to FIGS. 12 and 13.
(1) First, as shown in FIG. 12(a), V-grooves 502 with a desired depth are formed on the main surface of a single crystalline Si substrate (wafer) 501 with, for instance, (100) crystal orientation planes, by employing an anisotropic etching technology.
It is to be noted that in order to prevent the single crystalline Si substrate 501 from being damaged by the presence of the V-grooves 502, it is desirable to provide an LSI chip 506 pattern layout which uses an orientation flat 501A for reference on the single crystalline Si substrate 501 to ensure that no grooves are formed on the circumferential edge portion of the single crystalline Si substrate 501.
(2) Next, as illustrated in FIG. 12(b), an embedded diffusion layer 503 with the same conduction type as that of the single crystalline Si substrate 501, and then an isolation insulating film 504, separating the individual elements, are formed at the main surface of the single crystalline Si substrate 501 where the V-grooves 502 have been formed.
(3) Next, as illustrated in FIG. 12(c), a polycrystalline Si layer 505 is formed on the single crystalline Si substrate 501 via the isolation insulating film 504. This polycrystalline Si layer 505 is required to have a thickness which is at least large enough to fill the V-grooves 502, and the thickness is normally set at twice the depth of the V-grooves 502.
(4) Next, as illustrated in FIG. 12(d), the polycrystalline Si layer 505 is removed down to the position indicated with line A--A (see FIG. 12(c)) so that the surface of the polycrystalline Si layer 505 extends parallel to the bottom surface of the single crystalline Si substrate 501. Then, by performing a mirror treatment on the main surface of the polycrystalline Si layer 505, a mirror finished surface 506 with a maximum surface roughness of 500 .ANG. is formed.
(5) Next, as illustrated in FIG. 13(a), the main surface of a supporting substrate 508 upon which a 0.5 .mu.m oxide film 507 is formed, and the main surface of the single crystalline Si substrate 501 with the polycrystalline Si layer 505 having had the mirror finish treatment performed on its main surface, arc cleaned and activated. After this, the main surfaces of the supporting substrate 508 and the single crystalline Si substrate 501 are pressed into close contact for bonding.
During this pressing step, defective contact, i.e., the formation of so-called voids, is normally prevented by using a supporting jig 517 to gradually press the main surfaces together from one corner of the substrate, i.e., from the side of the semiconductor substrate 501 with the orientation flat 501A, for instance, as illustrated in FIG. 15.
Next, by performing high temperature heat treatment at, for instance, 1200.degree. C. for two hours, a bonded substrate 509 is formed.
(6) Next, as illustrated in FIG. 13(b), by polishing the main surface of the single crystalline Si substrate 501 at the opposite side down to the position indicated by the line B--B (see FIG. 13(a)), a dielectric isolation substrate 511 provided with single crystalline Si islands 510 which are isolated from one another is formed.
However, with the manufacturing method for a dielectric isolation substrate in the prior art described above, during the mirror finish step performed on the polycrystalline Si layer 505 illustrated in FIG. 12(d), a depression 505A of approximately 100 .ANG. is formed at the polycrystalline Si layer on a V-groove 502, as indicated within the circle in an enlargement of the central portion shown in FIG. 16, due to the difference between the orientation of the flat portion of the semiconductor substrate 501 and the polycrystalline Si layer 505 on the V-groove 502. The depth of the depression 505A becomes more pronounced as the V-groove 502 becomes deeper.
Then, during the pressing step for the single crystalline Si substrate 501 and the supporting substrate 508 illustrated in FIG. 15, the speed at which pressing is performed is reduced in the area where the depression 505A is formed compared to the flat area as the depth of the depression 505A becomes greater and also as the pattern ratio of the depression 505A becomes larger. Because of this, as shown in FIG. 17, in the LSI chip pattern area 506, which is formed on the single crystalline Si substrate 501 with the depression 505A, the speed at which the pressing is performed is reduced compared to that in the flat areas at the circumferential edge portion where there is no pattern (the lengths of the arrows in the figure indicate the pressing speed), sometimes resulting in a small void (unbonded portion) 507 remaining within the LSI chip area.
Although such voids do not normally cause problems such as separation of an LSI chip during the wafer production process, they are listed as one of the causes of chip separation during subsequent assembly processes, constituting a cause for reduced yield.
In order to avoid formation of such voids and to achieve a more stable bonded structure, Japanese Unexamined Patent Publication No. 1994-151572, for instance, discloses a method whereby a polycrystalline silicon layer is constituted as a two-fold structure to fill the voids during the heat treatment for bonding.
However, even when this method is employed, formation of voids in the LSI chip pattern area is not entirely prevented. Also, the number of steps is increased.